This invention relates to a step-up circuit which uses a charge pump to provide a higher voltage than its power source.
Among the recently developed semiconductor devices are multi-functional one-chip microcomputers and the like containing circuits such as EPROMs and EEPROMs which require for their operation a high voltage of about 20V. In order to make them easier to use, however, they should be designed to depend on only one power source such as a single 5V power line. In other words, such a device must include within itself a step-up circuit to generate a higher voltage from a lower-voltage power source.
An example of step-up circuit using a charge pump is shown in FIG. 2A wherein .phi. and .phi. indicate clock signals which have mutually opposite phases as shown in FIG. 2B. The charge pump is comprised of an array of m (=an integer greater than 1) transfer transistors Tr.sub.1, . . . Tr.sub.m and, if they are sequentially numbered from 1 to m for convenience, the mutually opposite clock signals .phi. and .phi. are applied respectively to the even-numbered and odd-numbered ones of them through parallel-connected capacitors C.sub.1, . . . C.sub.m as shown such that each of these capacitors serves to step up the voltage transmitted from one to the next of the transfer transistors in the array to provide a higher voltage V.sub.PP from a lower source voltage V.sub.DD. More in detail, if V.sub.i (i=1, . . . m) each indicate the voltage of the junction point between two mutually adjacent transistors as shown in FIG. 2A and V.sub.th is the transistors' threshold voltage, V.sub.1 =V.sub.DD -V.sub.th when the first clock signal .phi. is in a high voltage state. Thereafter, when the voltage of the second clock signal .phi. rises, the voltage V.sub.1 is stepped up to 2V.sub.DD -V.sub.th by the first capacitor C.sub.1. This switches on the first transfer transistor Tr.sub.1 and the voltage V.sub.2 becomes 2V.sub.DD -2V.sub.th and thereby charges up the second capacitor C.sub.2. When the voltage of the first clock signal .RTM. rises again next, the voltage V.sub.2 is increased to 3V.sub. DD -2V.sub.th by the second capacitor C.sub.2, thereby switching on the second transfer transistor Tr.sub.2. This, in turn, causes the voltage V.sub.3 to rise to the level of 3V.sub.DD -3V.sub.th. In this manner, the voltages V.sub.1, V.sub.2, . . . are increased thereafter in synchronism with the clock signals and a high voltage V.sub.PP is finally obtained.
With a step-up circuit thus structured, a high voltage is supplied by charging up a final-stage capacitor C when the second clock signal .phi. is in a high-voltage period. If the consumption of the high-voltage current therefrom grows abnormally during a low-voltage period of the second clock signal .phi., however, the high-voltage level is caused to either fluctuate or become lower. In other words, since the desired high voltage is supplied only through the final-stage capacitor C, the final-stage transfer transistor Tr.sub.m is switched on if V.sub.PP drops. This has the effect of lowering the voltage V.sub.m and the lowering of this voltage V.sub.m similarly has the effect of lowering the voltages at junctions on the upstream side. As a result, efficiency of the step-up circuit is very adversely affected.